A modified MixColumn-InversMixColumn in AES algorithm suitable for hardware implementation using FPGA device
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Abstract
This article described the Advanced Encryption Standard (AES) encryption and decryption process without using lookup tables in the MixColumns transformation and parallelizing the transformation process implemented in the Field Programmable Gate Array (FPGA) hardware. Parallelism of the hardware process conducted to the transformation of key schedule, addroundkey, subbyte and shiftrows (subshift) and mixcolumns in the first 5 rounds of the encryption process. The decryption process was parallelized in subshift transformations, both transformations were implemented at the same time. This research produced a modified AES encryption and decryption method and algorithm with the aim of minimizing the resources required for hardware implementation. The method in this article was applied to Xilinx ISE 14.7 software. The experimental results showed that the encryption process required 2,357 slice LUT's, 845 occupied slices and 26 IOB's, while the decryption process required 2,896 LUT's, 1,323 occupied slices and 26 IOB's resources. The encryption and decryption processes each took an average of 2.891 nanoseconds and 3.467 nanoseconds for every 128 bits of data. This approach leads us to obtain a component with minimum resources and enough computational speed.
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References
2. A. Muslim Djamalilleil, M. Salim, Y. Alwi and H. Herman, Modified Transposition Cipher Algorithm for Images Encryption, The 2nd east Indonesia conference on computer and information technology (Eiconcit Makassar, South Sulawesi, (2018) 1-4.
3. Mu. Annalakshmi and A. Padmapriya, Zigzag Ciphers: A Novel Transposition Method, IJCA Proceedings on International Conference on Computing and information Technology 2013 IC2IT(2), (2013) 8-12.
4. C.A. Murugan, P. Karthigaikumar and S.S. Priya, FPGA Implementation Of Hardware Architecture With AES Encryptor Using Sub-Pipelined S-Box Techniques For Compact Applications, AUTOMATIKA, 61(4) (2020) 682–693.
5. P. Poonia and P. Kantha, Comparative Study of Various Substitution and Transposition Encryption Techniques, Int. J. Comput. Appl., 145(10) (2016) 24-27.
6. E. Barker, Guideline for Using Cryptographic Standards in the Federal Government:Cryptographic Mechanisms, NIST Special Publication 800-175B Revision 1, (2020).
7. I.C. Guzmán, R.D. Nieto and Á. Bernal, FPGA implementation of the AES-128 algorithm in non-feedback modes of operation, Dyna, 83(198) (2016) 37-43.
8. U. Farooq, and M. Faisal Aslam, Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA, J. King Saud Univ., 29( 3) (2017) 295-302.
9. P. Vijayakumar, P.L. Kishore, K.V.D. Reddy, S. Reddy, R. Rajashree and A. Durai, FPGA Implementation of High Speed AES Based Authentication Algorithm, JAT, 12(7) (2020) 112-126.
10. L. Zhao and D. Lie, Is Hardware More Secure Than Software?, IEEE Security & Privacy, 18(5) (2020) 8-17.
11. S. Soni, Himani Agrawal, dan Dr. (Mrs.) Monisha Sharma, Analysis and Comparison between AES and DES Cryptographic Algorithm, IJEIT, 2(6) (2012) 17-20.
12. N. G. Augoestien and A. E. Putra, Purwarupa perangkat keras untuk eksekusi algoritma aes berbasis fpga (Hardware Prototype for AES Algorithm Based on FPGA), IJEIS, 5(2) (2015) 211–220.
13. M. Sleem, Yousra Alakabani, Ali Rashed and Attif Ibraheem, Low Power Implementation of AES Mix Columns/ Inverse Mix Column on FPGA, Adv. Mat. Res., Trans Tech Publications, Ltd, 677 (2013) 311-316..
14. S. Ghaznavi, Catherine Geboty and Reoven Elbaz, Efficient technique for the FPGA implementation of the AES Mix columns Transformation, International conference on Reconfigurable Computing and FPGAs, (2009) pp.219-224.
15. V. Fischer, Milos Drutarovsky and Pawel Chodowiec, InvMixcolumn Decomposition and Multilevel Resource Sharing in AES Implementation, in IEEE Trans. On VLSI Systems, 13(8) (2005) 989-992.
16. A. Berent, Advanced Encryption Standard by Example, Document available at URL https://www.adamberent.com/wp-content/uploads/2019/02/AESbyExample.pdf Accessed: May 2021.
17. H. Zodpe and A. Sapkal, An efficient AES implementation using FPGA with enhanced security features, J. King Saud Univ., 32(2) (2020). 115-122.
18. Q. Zhang, Qunding, Digital Image Encryption Based On Advanced Encryption Standard (AES) Algorithm, 2015 Fifth International Conference on Instrumentation and Measurement, Computer, Communication and Control, (2015) 1218-1221.
19. Y. J. Liand and W. L. Wu, Improved Integral Attacks on Rijndael C, J. Inf. Sci. Eng., 27(6) (2011) 2031- 2045.
20. Y. W. Zhu,H. Q. Zhang, Y. B. Bao, Study of the AES Realization Method on the Reconfigurable Hardware C, 2013 International Conference on Computer Sciences and Applications, (2013) 72-76.
21. J. Toldinas, V. Stuikys, R. Damasevicius, G. Ziberkas and M. Banionis, Energy Efficiency Comparion with Cipher Strength of AES and Rijndael Cryptographic Algorithms in Moble Devices, J. Elektonika IR Elektrotechnika, 108( 2) (2011) 11-14.
22. F. Wegener, L.D. Meyer and A. Moradi, Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version, J. Cryptol., 33 (2020) 1114-1155.
23. M. Kumar, Senthil and DR. S. Rajalakshmi, High Efficient Modified MixColumns in Advanced Encryption Standard using Vedic Multiplier, International Conference on Current Trends in Engineering and Technology (ICCTET), (2014) 462-466.
24. N.E. Abraham and Tibin Thomas, FPGA Implementation of Mix and Inverse Mix Column for AES Algorithm, IJSRD, 1(9) 2321-0613..
25. C. Nalini, P.V. Anandmohan, D.V. Poornaiah and V.D. Kulkami, Compact Designs of SubBytes and MixColumn for AES, IEEE International Advance Conputing Conference, (2009) 1241-1247.
26. Y. Kurniawan & M. A. Rizqulloh, Block cipher four implementation on field programmable gate array, Commun.Sci. Technol, 5(2) (2020) 53-64.