Block cipher four implementation on field programmable gate array

Article Sidebar

PDF
DOI: https://doi.org/10.21924/cst.5.2.2020.184
Keywords:
BCF, FPGA, NIOS II, Cryptography

Main Article Content

Yusuf Kurniawan
Institut Teknologi Bandung
Muhammad Adli Rizqulloh
Universitas Pendidikan Indonesia

Abstract

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

Downloads

Download data is not yet available.

Article Details

How to Cite
Kurniawan, Y., & Rizqulloh, M. A. (2020). Block cipher four implementation on field programmable gate array. Communications in Science and Technology, 5(2), 53-64. https://doi.org/10.21924/cst.5.2.2020.184
Issue
Vol. 5 No. 2 (2020)
Section
Articles
Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Copyright

Open Access authors retain the copyrights of their papers, and all open access articles are distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution and reproduction in any medium, provided that the original work is properly cited.

The use of general descriptive names, trade names, trademarks, and so forth in this publication, even if not specifically identified, does not imply that these names are not protected by the relevant laws and regulations.

While the advice and information in this journal are believed to be true and accurate on the date of its going to press, neither the authors, the editors, nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein.

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.

Crossref
Scopus
Google Scholar
Europe PMC

References

1. Y. Kurniawan. The BCF block cipher design, Technical Report, Institut Teknologi Bandung, Indonesia, 2018.
2. Ma'muri, Y. Kurniawan and S. Sutikno, Implementation of BC3 encryption algorithm on FPGA Zynq-7000, Int. Symp. Electronics Smart Devices, Yogyakarta, Indonesia, 2017, pp. 329-334.
3. Hua Li and Z. Friggstad, An efficient architecture for the AES mix columns operation, IEEE Int. Symp. Circuits Syst., Kobe, 2005, pp. 4637-4640.
4. S. Ghaznavi, C. Gebotys and R. Elbaz, Efficient technique for the FPGA implementation of the AES mixcolumns transformation, Int. Conf. Reconfigurable Computing FPGAs, Quintana Roo, 2009, pp. 219-224.
5. A. O. Adebayo, M. S. Chaubey, and L. P. Lumbu, Industry 4.0: The fourth industrial revolution and how it relates to the application of internet of things(IoT), J. Multidisciplinary Eng. Sci. Studies 5 (2019) 2477-2482.
6. I. A. Landge and H. Satopay, Secured IoT through hashing using MD5, Fourth Int. Conf. Adv. Electric., AEEICB, Chennai, 2018, pp. 1-5.
7. S. D. Putra, M. Yudhiprawira, Y. Kurniawan, S. Sutikno and A. S. Ahmad, Security analysis of BC3 algorithm for differential power analysis attack, Int. Symp. Electronics Smart Devices (ISESD), Yogyakarta, 2017, pp. 341-345.
8. P. C. Kocher. Timing attacks on implementations of diffie-hellman, RSA, DSS, and other systems. In: Koblitz N. (eds) Advances in Cryptology — CRYPTO ’96. Lecture Notes in Computer Science, Springer, Berlin, Heidelberg, 1996.
9. Altera, DE2-115 cyclone II development board user manual, Altera, 2010
10. A. Laboratory, Cryptographic hardware project: IP core, http://www.aoki.ecei.tohoku.ac.jp/crypto/web/cores.html, 2019.
11. W. Stalling. Cryptography and network security principles and practices(4th ed). New Jersey: Prentice Hall, 2005.
12. P. S. L. M. Barreto and V. Rijmen. The Khazad Legacy-level Block Cipher, NESSIE, 2001.
13. A. E. Standard., Federal Information Processing Standards Publication, FIPS PUB 197, 2001.
14. K. Aoki, T. Ichikawa, M. Kanda, M. Matsui, S. Moriai, J. Nakajima, T. Tokita,Specification of camellia — a 128-bit block cipher, NTT and Mitsubishi Electric Corporation 2000-2001, 2001, pp. 1-35.
15. B. Schneier, J. Kelsey, D. Whiting, D. Wagner, C. Hall, N. Ferguson, Twofish: a 128-bit block cipher. Proceedings first AES cand. conf., 1998.
16. A. Sideris, T. Sanida and M. Dasygenis, Hardware acceleration of the AES algorithm using Nios-II processor, Panhellenic Conf. Electronics Telecommunications, Volos, Greece, 2019, pp. 1-5.
17. R. Mahmoud, T. Yousuf, F. Aloul and I. Zualkernan, Internet of things (IoT) security: Current status, challenges and prospective measures, 10th Int. Conf. Internet Tech. Secured Transactions, London, 2015, pp. 336-341.